Phase change memory device having a uniform set and reset current

ABSTRACT

A phase change memory device having a uniform set and reset current includes a first and second sense amplifiers that are respectively placed adjacent to both ends of a plurality of active regions. The active regions include a first active region and a second active region. The first active region has a first area having a first width, a second area having a second width greater than the first width, and a third area having a third width greater than the second width and are sequentially arranged in a direction extending toward an area adjacent to the first sense amplifier. The second active region has a first area having a first width, a second area having a second width greater than the first width, and a third area having a third width greater than the second width, which are sequentially arranged in a direction extending toward an area adjacent to the second sense amplifier.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to Korean patent applicationnumber 10-2006-0113469 filed on Nov. 16, 2006, which is incorporatedherein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a phase change memory device, and moreparticularly, to a phase change memory device that allows a plurality ofmemory cells of a memory array to be programmed with the same resetcurrent and the same set current.

In general, memory devices are largely categorized as a volatile RAM(random access memory) that loses stored information when power isinterrupted and a non-volatile ROM (read-only memory) that cancontinuously maintain the stored state of information even when power isinterrupted. Volatile RAM includes memory such as DRAM (dynamic RAM) andSRAM (static RAM) whereas non-volatile ROM includes a flash memorydevice such as an EEPROM (electrically erasable and programmable ROM)can be mentioned.

As is well known in the art, although the DRAM is an excellent memorydevice, the DRAM must have a high charge storing capacity. To this end,since the surface area of an electrode must be increased, it isdifficult to obtain a high integration level. Further, in a flash memorydevice, a high operation voltage is required when compared to a sourcevoltage due to the fact that two gates are stacked on each other.Accordingly, since a separate booster circuit is needed to form thevoltage necessary for write and delete operations, it is difficult toaccomplish a high integration level.

Due to these limitations, research to develop a novel memory devicehaving a simple configuration capable of accomplishing a high level ofintegration while retaining the characteristics of a non-volatile memorydevice have been pursued. For example, recently, a phase change memorydevice has been disclosed in the art.

The phase change memory device is based on the fact that a phase changeoccurs in a phase change layer interposed between a lower electrode andan upper electrode from a crystalline state to an amorphous state due tocurrent flow between the lower electrode and the upper electrode. Theinformation stored in a cell is recognized by the medium of a differencein resistance between the crystalline state and the amorphous state.

The phase change memory device includes a chalcogenide layer which is acompound layer made of germanium (Ge), stibium (Sb) and tellurium (Te)that is employed as a phase change layer. As a current is applied, thephase change layer undergoes a phase change between the amorphous stateand the crystalline state due to heat, specifically Joule heat.Accordingly, in the phase change memory device, the specific resistanceof the phase change layer in the amorphous state is higher than thespecific resistance of the phase change layer in the crystalline state.Considering this fact, in a read mode, sensing the current flowingthrough the phase change layer determines whether the information storedin the phase change cell has a logic value of ‘1’ or ‘0’.

Meanwhile, in a memory array having a plurality of memory cells, theparasitic loadings of the respective memory cells can be different fromone another according to the locations of the memory cells in the memoryarray. The parasitic loadings induce differences in the reset currentsof the memory cells as the area of the memory array increases. Thesedifferences in the rest currents may also cause differences in setcurrents.

Due to the differences in set currents, all the memory cells cannot beuniformly set by one set current. That is to say, while some of thememory cells transition to a set state by the set current, other memorycells can be in a reset state. Even where some of the memory cellstransition to the set state, the values of set resistances can bedifferent from one another.

FIG. 1 is a graph illustrating a relationship between the currentapplied to phase change cells and the resistances of the phase changecells in a conventional phase change memory device.

Referring to FIG. 1, respective memory cells have different reset andset current curves. The first cell has a high set current, the secondcell has an intermediate set current, and the third cell has a low setcurrent.

If the current corresponding to a voltage level (V) is applied to therespective cells, the second cell and the third cell transition to resetresistance states. The values of the reset resistances of the second andthird cells are also different from each other.

Therefore, as described above, in a plurality of memory arrays, theamount of set current for transitioning the phase change cells to a setstate may vary in respective memory cells. Thus, all the memory cellsmay not transition to the set state by one set is current.

The differences in the amount of set current for the memory cells aregenerally observed between the cell (a first cell) closest to a senseamplifier and the cell farthest from the sense amplifier (an n^(th)cell). In the case of the first cell, the first cell can beover-programmed when compared to the n^(th) cell, and in the case of then^(th) cell, the n^(th) cell may not be programmed.

SUMMARY OF THE INVENTION

Embodiments of the present invention are directed to a phase changememory device that allows a plurality of memory cells of a memory arrayto be programmed with the same reset current and the same set current.

In one embodiment of the present invention, a phase change memory devicecomprises a semiconductor substrate having a plurality of active regionswhich extend in one direction and are arranged in another direction; aplurality of word lines formed on the active regions to extend inanother direction; source areas and drain areas formed in the activeregions on both sides of the word lines; a plurality of phase changecells formed to contact the source areas, and the phase change cellsincluding lower electrodes, phase change layers and upper electrodes; aplurality of bit lines arranged to extend in one direction which isperpendicular to the word lines, and formed to contact the upperelectrodes of the phase change cells; and sense amplifiers connectedwith the bit lines, wherein the sense amplifiers include a first senseamplifier and a second sense amplifier which are respectively placedadjacent to one end and the other end of the active regions, wherein thebit lines include first bit lines which are connected with the firstsense amplifier and second bit lines which are connected with the secondsense amplifier, and the first and second bit lines are alternatelyarranged with each other, and wherein the active regions include a firstactive region and a second active region, the first active region has afirst area having a first width, a second area having a second widthgreater than the first width, and a third area having a third widthgreater than the second width, which are sequentially arranged in adirection extending toward an area adjacent to the first senseamplifier, and the second active region has a first area having a firstwidth, a second area having a second width greater than the first width,and a third area having a third width greater than the second width,which are sequentially arranged in a direction extending toward an areaadjacent to the second sense amplifier.

A border area between the first area and the second area and a borderarea between the second area and the third area are sequentiallyarranged while having an acute angle.

A border area between the first area and the second area and a borderarea between the second area and the third area are sequentiallyarranged while having a right angle.

Each of the first active region and the second active region has astructure in which a plurality of areas having widths greater than thethird width are sequentially arranged with one another.

The first area, the second area and the third area are sequentiallyarranged while being separated from one another.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a graph illustrating a relationship between the currentapplied to phase change cells and the resistances of the phase changecells in a conventional phase change memory device.

FIGS. 2A through 2C are plan views explaining a phase change memorydevice in accordance with an embodiment of the present invention.

FIG. 3 is a plan view explaining a phase change memory device inaccordance with another embodiment of the present invention.

FIG. 4 is a plan view explaining a phase change memory device inaccordance with still another embodiment of the present invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

In an embodiment of the present invention, all the memory cells of amemory array can be programmed with the same set current and the samereset current by differentiating the channel widths of cells between achannel length and a channel width that determine the current amount ofa transistor. In other words, in an embodiment of the present invention,a near cell (corresponding to a first region), which is close to a senseamplifier, has a decreased width of a transistor, a medium cell(corresponding to a second region), which is intermediately positioned,has an average width of a transistor, and a far cell (corresponding to athird region), which is distant from the sense amplifier, has anincreased width of a transistor.

As a result, in the phase change memory device according to anembodiment of the present invention, since the current amounts appliedto a phase change material by one set current or reset current are thesame, the parasitic loading of the far cell which is distant from thesense amplifier is compensated for and therefore the same set resistanceand the same reset resistance can be accomplished.

In detail, FIGS. 2A through 2C are plan views explaining a phase changememory device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, a semiconductor substrate is formed to have aplurality of active regions 200, in which each active region 200 extendsin one direction while the plurality of the active regions 200 arearranged in another direction. The plurality of active regions 200include a first active region 210 and a second active region 220. In thefirst active region 210, a first area 201 having a first width W1, asecond area 202 having a second width W2 that is greater than the firstwidth W1, and a third area 203 having a third width W3 that is greaterthan the second width W2 are sequentially arranged. The second activeregion 220 has a shape corresponding to that of the first active region210. In the second active region 220, a first area 201, a second area202 and a third area 203 are sequentially arranged in a reverse order inrelation to the first active region 210. The surfaces of the first andsecond active regions 210 and 220 that face away from each other have astraight-line sectional shape. The pair of first and second activeregions 210 and 220, which face each other, are formed in a pluralnumber.

The first active region 210 and the second active region 220 are formedsuch that the border area between the first area 201 and the second area202 has an acute angle r°. The border area between the second area 202and the third area 203 also has acute angle r°. The border areas betweenfirst and second active regions 201 and 202, respectively, and secondand third active regions 202 and 203, respectively are sequentiallyarranged. A first sense amplifier S/A.1 and a second sense amplifierS/A.2 are placed adjacent to opposite ends of the active regions 200.The first sense amplifier S/A.1 is placed adjacent to the first activeregion 210 and the second sense amplifier S/A.2 is placed adjacent tothe second active region 220.

Therefore, the first active region 210 has a structure in which thefirst area 201, the second area 202 and the third area 203 aresequentially arranged in a direction extending toward the area adjacentto the first sense amplifier S/A.1. Also, the second active region 220has a structure in which the first area 201, the second area 202 and thethird area 203 are sequentially arranged in a direction extending towardthe area adjacent to the second sense amplifier S/A.2.

Meanwhile, although not shown in the drawings, each of the first activeregions 210 and the second active regions 220 can have a structure inwhich a plurality of areas having widths greater than the third width W3are sequentially arranged.

In an embodiment of the present invention, where the first area (a nearcell) 201, the second area (a medium cell) 202 and the third area (a farcell) 203 are formed to have different widths in the direction extendingtoward the area adjacent to the sense amplifier, all cells can beprogrammed with the same set current and same reset current by varyingthe width of a transistor which determines the current amount of thetransistor.

In other words, the first active region 210 adjoining the first senseamplifier S/A.1 is formed to have a structure in which the first area201 having the first width W1, the second area 202 having the secondwidth W2 that is greater than the first width W1, and the third area 203having the third width W3 that is greater than the second width W2 aresequentially arranged in a direction extending towards the first senseamplifier S/A.1. The second active region 220 adjoining the second senseamplifier S/A.2 has a shape corresponding to that of the first activeregion 210 and is formed to have a structure in which the first area201, the second area 202 and the third area 203 are sequentiallyarranged in a direction extending towards the second sense amplifierS/A.2. Since the current amounts applied to a subsequently formed phasechange material by one set current or reset current becomes uniformlythe same, the parasitic loadings owned by the third areas (the farcells) 203 which are most distant from the first and second senseamplifiers s/A.1 and S/A.2 is compensated for, whereby a sensing margincan be increased.

Referring to FIG. 2B, a plurality of word lines 230 are formed on theactive regions extending in a direction perpendicular to the activeregions. A transistor is configured by forming a source area and a drainarea (not shown) on both sides of each word line 230.

While not shown in detail in the drawings, a plurality of phase changecells including lower electrodes, phase change layers, and upperelectrodes are formed to come into contact with respective source areas.

Referring to FIG. 2C, a plurality of bit lines 240 are formed to extendin one direction perpendicular to the word lines 230 and to contact theupper electrodes of the phase change cells.

In the above-described embodiment, the active region is formed in amanner such that the border area between the first area 201 and thesecond area 202 and the border area between the second area 202 and thethird area 203 are sequentially arranged having an acute angle r°.However, in another embodiment of the present invention, as shown inFIG. 3, an active region can be formed in a manner such that the borderarea between a first area 301 and a second area 302 and the border areabetween the second area 302 and a third area 303 are sequentiallyarranged having a right angle s°. In FIG. 3, reference numeral 310designates a first active region and 320 a second active region.

Also, in the above-described embodiment, the first area 201, the secondarea 202 and the third area 203 are sequentially arranged without beingseparated from one another. However, in still another embodiment of thepresent invention, as shown in FIG. 4, a first area 401, a second area402 and a third area 403 of an active region can be formed in a mannersuch that they are sequentially arranged while being separated from oneanother. In FIG. 4, reference numeral 410 designates a first activeregion and 420 a second active region.

As is apparent from the above description, in the phase change memorydevice according to an embodiment of the present invention, where alength and a width determines the current amount of a transistor, thechannel widths of transistors are differentiated. Namely, a near cellclose to a sense amplifier, has a decreased width of a transistor, amedium cell, which is intermediately positioned, has an average width ofa transistor, and a far cell, which is distant from the sense amplifier,has an increased width of a transistor. Therefore, all the cells can beprogrammed with the same set current and the same reset current.

As a result, in an embodiment of the present invention, the parasiticloading of the far cell that is distant from the sense amplifier iscompensated and the same set resistance and the same reset resistancemay be accomplished.

Although specific embodiments of the present invention have beendescribed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and the spirit of theinvention as disclosed in the accompanying claims.

1. A phase change memory device comprising: a semiconductor substratehaving a plurality of active regions, each of which extending in onedirection, and the plurality of active regions being arranged in anotherdirection; a plurality of word lines formed on the active regions toextend in another direction; a plurality of source areas and drain areasformed in the active regions on both sides of the word lines; aplurality of phase change cells formed to contact the source areas, thephrase change cells comprising: lower electrodes, phase change layersand upper electrodes; a plurality of bit lines arranged to extend in onedirection that is perpendicular to the word lines, and formed to contactthe upper electrodes of the phase change cells; and sense amplifiersconnected with the bit lines, wherein the sense amplifiers include afirst sense amplifier and a second sense amplifier which arerespectively placed adjacent a first end of the active regions and asecond end of the active regions opposite the first end, wherein the bitlines include first bit lines which are connected with the first senseamplifier and second bit lines which are connected with the second senseamplifier, wherein the first and second bit lines are alternatelyarranged with each other, and wherein the active regions include a firstactive region and a second active region, the first active region has afirst area having a first width, a second area having a second widthgreater than the first width, and a third area having a third widthgreater than the second width, which are sequentially arranged in adirection extending toward an area adjacent to the first senseamplifier, and the second active region has a first area having a firstwidth, a second area having a second width greater than the first width,and a third area having a third width greater than the second width,which are sequentially arranged in a direction extending toward an areaadjacent to the second sense amplifier.
 2. The phase change memorydevice according to claim 1, wherein a border area between the firstarea and the second area and a border area between the second area andthe third area are sequentially arranged while having an acute angle. 3.The phase change memory device according to claim 1, wherein a borderarea between the first area and the second area and a border areabetween the second area and the third area are sequentially arrangedwhile having a right angle.
 4. The phase change memory device accordingto claim 1, wherein each of the first active region and the secondactive region has a structure in which a plurality of areas havingwidths greater than the third width are sequentially arranged with oneanother.
 5. The phase change memory device according to claim 1, whereinthe first area, the second area and the third area are sequentiallyarranged while being separated from one another.